Stacked capacitors often find application in integrated circuits, the down-sizing of which is continually being sophisticated. The demand for ever-smaller chip sizes is not easy to satisfy because of the necessary dimensions of the passive components of the circuits. The approaches to date to enhancing the performance of stacked capacitors per component volume unit are as follows:                Reducing the thickness of conventional dielectrics such as silicon oxide or silicon nitride. Such a reduction necessitates, however, better control in depositing the dielectrics, especially as regards their thickness and defects. In addition, a better material quality is needed to meet the requirements as to component lifetime. In prior art, high-temperature LPCVD processes have proven to be superior to low-temperature PECVD processes. When, however, capacitors including plates are provided integrated in metallization layers (aluminum), the temperature must not exceed a critical limit because of the structural integrity requirements of the metallization layers. Apart from this, low-temperature processes are given preference when diffusion-prompted changes in the silicon doping profiles are to be avoided. For reliability reasons, the capacitive density for dielectrics deposited in a PECVD process, is typically restricted to 1.5 fF/μm2 (oxide) and 3 fF/μm2 (nitride).        Using dielectrics having a high dielectric constant. Making use of materials such as titanium dioxide (TiO2), tantalum pentoxide (Ta2O5) or barium strontium titanate (BaxSr1-xTiO3) would appear to be very promising because of the relatively high dielectric constants, but is not yet established. The majority of these materials have a high leakage current rate and component fabrication is highly problematic. Acceptable breakdown and leakage properties are achievable hitherto only with relative thick films preventing advantageous use of the superior dielectric properties of these materials. Apart from this, introducing these new materials necessitates creating additional clean room space for new hardware and new chemicals as well as added complications in production planning, all of which adds to the production costs. Integrating fabrication in an existing process line likewise involves changes in the technology architecture.        Exploiting the vertical chip dimension to enhance the effective surface area of a capacitor. Providing a suitable topography making better use of the vertical dimension of a component necessitates the development of new patterning processes and/or the introduction of additional masking layers. Furthermore, additional process requirements such as critical dimension (CD) control, etching selectivity, step coverage and planarity need to be satisfied. Application of this kind of structures is often restricted by the requirements of the particular applications. Due to the change in the vertical geometry, the series resistance of the capacitor films is increased, resulting in a lower Q of the capacitor, making it unsuitable for certain high-frequency applications. Precision and adaptability are limited by the lithographic and etching possibilities, likewise the variation in the vertical thickness.        
In integrated circuits comprising interlinked layers the capacitive density can be enhanced by stacking two (or more) conventional capacitors by simply reproducing the same structure on different metallization layers. However, the costs for introducing an additional metallization layer and various other patterning steps in a process line continue to be unjustified until the investment needed for chip size reduction is compensated by a higher yield and a commensurate integrated circuit qualification rate.
In the ever-increasing integration of many components into a single integrated circuit it is desirable to use the same type of capacitor for several applications, e.g. for high-frequency or ultra-precision analog applications. For blocking capacitors having a very high capacitance, preference is given to silicon nitride as the dielectric material because of its high dielectric constant. Capacitors used in ultra-precision analog applications necessitate, however, a much better linearity and frequency independency, resulting in silicon oxide with its lower dielectric constant being the best choice. In such conflicting requirements the process line permits optimizing only for the one or the other application, resulting in a compromise as regards product performance as a whole. As an alternative, in meeting customer requirements, two different capacitor types having the same technology can be made available which, however, adds to the costs and complexity of the process line.